The present invention relates to error performance analyzers. This application for patent is a continuation-in-part of Ser. No. 09/723,821 an application filed on Nov. 28, 2000, titled xe2x80x9cMethod And Apparatus For Displaying Triggered Waveform On An Error Performance Analyzerxe2x80x9d, Attorney Docket No. 10003986-1. More specifically, the present invention relates to the method and apparatus for displaying waveforms of binary digit transmission using error performance analyzers.
A fundamental measure of quality of digital circuits, switches, and transmission systems is the probability of any stored or transmitted bit being transmitted in error, or bit error ratio (BER). The BER is typically tested using a bit error ratio tester (BERT) which may include of a pattern generator and an error detector. The pattern generator and the error detector are often combined in a single unit though this is not required. They are, in fact, sometimes separate units. The pattern generator generates a known sequence of bits (sequence of zeros and ones) for transmission through a device under test (DUT). Typically, the known sequence of bits is often generated by a pseudo-random bit sequencer (PRBS) and is of known length of 2Nxe2x88x921 bits where N may be any number. Commonly, numbers seven (7) or a ten (10) are used as the value of N. The known sequence of bits may be referred to as a base bit sequence, or a base bit pattern. The base bit pattern is continually repeated by the pattern generator.
The repeated base bit pattern is transmitted to the DUT which, in turn, transmits the bit sequences to be received by the error detector. The error detector compares the received bit sequence with the known bit sequence for error bit detection. Usually, the error detector also generates the known sequence of bits, or repeated base bit pattern, such that the error detector can compare the received bit sequence with the known bit sequence to detect errors in transmission. An error bit is a bit that is sent to the DUT as a zero but transmitted by the DUT as a one, or a bit that is sent to the DUT as a one but transmitted by the DUT as a zero. Then, the number of error bits is compared with the number of bits received. The ratio of the error bits to the sent bits is the bit error ratio, BER. With modern devices, the BER tends to be very low and can be on the order of 10xe2x88x9212 or even less.
As discussed, an error detector provides the BER as one measure of quality of the DUT. However, to determine digital waveform signal quality of any particular section of the base bit sequence, an oscilloscope is utilized to view the section in an eyeline mode. In eyeline mode, a pattern trigger that is synchronized with the repeating base bit sequence of the pattern generator is used to display a waveform of the selected section. The uses of the eyeline mode display the waveform diagram and the methods of generating the waveform diagram using an oscilloscope are known in the art.
In summary, to test a DUT for its error rate as well as to examine the quality of the waveform signal quality of the DUT, two devices are neededxe2x80x94an error detector and an oscilloscope. However, the use of the oscilloscope adds to the hardware requirements and costs to the DUT testing process. It would be preferable to display the waveform diagram using the error detector alone. Accordingly, there is a need for a technique and an apparatus to obtain the BER as well as to display the waveform diagram without the use of an oscilloscope.
These needs are met by the present invention. According to one embodiment of the present invention, a technique of displaying a waveform on an error performance analyzer is disclosed. A first bit sequence comprising repeated base bit pattern, each bit either a 0-bit signified by a first bit voltage, VLB, and 1-bit signified by a second bit voltage, VHB is received. Then, at a first time within the base bit pattern and each incremental time thereafter for a predetermined period of time, multivalue voltage, VM, is determined. Finally, the multivalue voltage at the first time and the multivalue voltage at each incremental time thereafter is displayed.
According to another embodiment of the invention, A first bit sequence comprising repeated base bit pattern, each bit either a 0-bit signified by a first bit voltage, VLB, and 1-bit signified by the a second bit voltage, VHB, is received. Then, at a first time within the base bit pattern and each incremental time thereafter for a predetermined period of time, multivalue voltage spread is determined. Finally, the multivalue voltage spread at the first time and the multivalue voltage spread at each incremental time thereafter is displayed.
According to yet another embodiment of the invention, an apparatus for displaying a waveform is disclosed. The apparatus has a processor and storage connected to the processor including instructions for the processor to receive a first bit sequence comprising repeated base bit pattern, each bit either a 0-bit signified by a first bit voltage, VLB, and 1-bit signified by a second bit voltage, VHB. Further, instructions include instructions for the processor to determine, at a first time within the base bit pattern and each incremental time thereafter for a predetermined period of time, multivalue voltage spread, VM-spread.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example, the principles of the present invention.